Most recent edit on 2007-07-12 06:47:47 by FaiF
Additions:
Now blackfin simulation only supports interpret-execution. We will add binary translation to speed up its execution in the future. You can spilt blackfin simulation module to two parts. The first part simulation the processor core and exists in arch/bfin/common directory, it simlates instruction-fetch, instruction-decode and instruction-excution. And all the instruction is exeucted step by step under interpret-execution way. The main excution cycle is in [ arch/bfin/common/bfin_arch_interface.c: bfin_step_once] .
The second part contain interrupt simulation and peripheral simuation and exists in arch/bfin/mach/ directory . It provides a bf533_io_do_cycle function for interrupt and exception detection.
Now only blackfin 533 processor is supported. Some features such as cache, cplb is not simulated until now.
Deletions:
[[http://people.msoe.edu/~millerni/forums.php?show=topic∞
Edited on 2007-07-05 05:33:49 by Mm4Xo8
Additions:
[[http://people.msoe.edu/~millerni/forums.php?show=topic∞
Deletions:
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The second part contain interrupt simulation and peripheral simuation and exists in arch/bfin/mach/ directory . It provides a bf533_io_do_cycle function for interrupt and exception detection.
Now only blackfin 533 processor is supported. Some features such as cache, cplb is not simulated until now.
Edited on 2007-07-04 13:02:36 by VrnFyj
Additions:
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Deletions:
Now blackfin simulation only supports interpret-execution. We will add binary translation to speed up its execution in the future. You can spilt blackfin simulation module to two parts. The first part simulation the processor core and exists in arch/bfin/common directory, it simlates instruction-fetch, instruction-decode and instruction-excution. And all the instruction is exeucted step by step under interpret-execution way. The main excution cycle is in [ arch/bfin/common/bfin_arch_interface.c: bfin_step_once] .
Edited on 2006-03-18 00:45:09 by 137.71.23.54
Additions:
Now blackfin simulation only supports interpret-execution. We will add binary translation to speed up its execution in the future. You can spilt blackfin simulation module to two parts. The first part simulation the processor core and exists in arch/bfin/common directory, it simlates instruction-fetch, instruction-decode and instruction-excution. And all the instruction is exeucted step by step under interpret-execution way. The main excution cycle is in [ arch/bfin/common/bfin_arch_interface.c: bfin_step_once] .
The second part contain interrupt simulation and peripheral simuation and exists in arch/bfin/mach/ directory . It provides a bf533_io_do_cycle function for interrupt and exception detection.
Now only blackfin 533 processor is supported. Some features such as cache, cplb is not simulated until now.
Deletions:
TODO
Oldest known version of this page was edited on 2005-12-02 21:18:37 by 137.71.23.54 []
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